1. Field of the Invention
This invention generally relates to digital communications and, more particularly, to a system and method using time-to-digital converters (TDCs) for generating digital phase-locked loop (PLL) error signals.
2. Description of the Related Art
Digital PLLs (DPLLs) are an area of active research and development. A DPLL performs the loop filtering function in the digital domain with synthesized logic. DPLLs provide several advantages over the analog PLLs, including easier and faster implementation, and better controllability of the PLL parameters. Also, the integrated circuit (IC) die area devoted to the circuitry and power consumption can be greatly reduced, especially in advanced fabrication processes. Therefore, there is a growing interest in DPLLs for high performance applications.
In a PLL based frequency synthesizer, the voltage controlled oscillator (VCO) clock is constantly compared with a reference clock. This comparison generates an error signal that is filtered and provided to the VCO, to correct the VCO frequency. In a charge pump PLL (CPPLL), a combination of phase/frequency detector (PFD) and charge pump perform phase error detection, and output an analog error signal. In DPLL, there is a need to convert this analog error signal to a digital error signal. One way of converting an analog signal to a digital signal is to utilize an analog-to-digital converter (A/D), but this approach requires additional power consumption and IC die area. A more practical approach would be to use a TDC to directly convert the phase offset to a digital error signal. A TDC can be used to digitize the duration of time between two events, usually represented by the edges of a signal. As described in more detail below, a TDC can be enabled with a delay line and sampling flip flops.
A key implementation challenge with the use of a TDC is the achievement a fine resolution error signal, in order to minimize the quantization noise effect on the PLL closed loop performance. However, a very fine resolution TDC usually has high, power consumption, making it unattractive compared to conventional charge pump architecture. Therefore, a major challenge associated with a TDC is the tradeoff between resolution and power consumption. For example, a 155 megahertz (MHz) reference clock and 5 picoseconds (ps) of resolution require more than 210 delay elements/samplers. It would be advantageous if a low-power TDC architecture could be used in DPLLs.
It would be advantageous if TDC power consumption could be minimized by significantly reducing the dynamic range requirements over which the TDC is expected to operate.